Since the development of integrated circuit technology, computers and computer storage devices have been made from integrated circuit (IC) chips formed from wafers of semiconductor materials. After a wafer is made, the ICs are typically separated from each other by dicing the wafer into small chips. Thereafter, the individual chips are bonded to carriers of various types, interconnected by wires and packaged. Such "two-dimensional" packages of chips fail to optimize the number of circuits that may be fabricated in a given space, and also introduce undesirable signal delays, capacitance, and inductance as signals travel between chips.
Recently, three-dimensional arrays of chips have emerged as an important packaging approach. The typical multi-chip electronic module consists of multiple IC chips adhesively secured together as a monolithic structure (a "plurality of stacked IC chips"). Corresponding edges of the integrated circuit chips, once stacked, form the substantially planar side surface of the electronic module. Transfer metallurgy from the active area of each integrated circuit chip extends to this side surface facilitating interconnection among the chips and/or external connection to the module. Often, a metallization pattern is provided directly on the side surface, connected to the transfer metallurgy. As used herein and known in the art, the term "transfer metal layer" refers to the metallization layer usually formed above the active surface of each chip subsequent to wafer fabrication.
One significant process step in the formation of an electronic module is the side surface processing necessary to electrically access the transfer metal leads presented to the side surface of the chip stack. When IC chips are defined on a wafer, "kerf" regions (spaces) exist between chips. These kerf regions facilitate separation ("dicing") of the chips without damaging the structures in the "active" region of the chip. After dicing, portions of these kerf regions remain on the chip between the edges of the chip and the active region, adjacent to each. Thus, in order to reach the edge of the chip, the transfer metallurgy must extend from the active region of the chip, and through the kerf region.
Typically, side surface processing entails etching the side surface of the module to expose the transfer metal leads. However, unless preferentially performed, such processing can expose other structures that exist in the kerf regions including chip metallurgy used in forming and testing the active region of the chip when still in wafer form. As used herein and known in the art, the "chip metal layer" is the metal layer(s) used in fabricating and interconnecting the functional active structures of an IC chip (for example, the bit lines, in a dynamic random access memory chip). An etchant is thus chosen which preferentially etches the side surface, including chip metallurgy, but not transfer metallurgy. This "preferential" etch is only possible if the chip metallurgy is different from the transfer metallurgy, enabling an etchant to operate on the chip metal but not the transfer metal. An insulating layer is then applied to the preferentially etched side face and planarized, covering the exposed structures (chip metallurgy), and exposing only the transfer metal leads. Electrical connection to the transfer metal leads may then be performed without danger of shorting to other structures such as a chip metal layer.
In order to completely remove the kerf region structures, several dry and wet etching techniques are often used. By their very nature, these etching processes entail very aggressive environments. Since these etching processes occur after lamination of the stack of IC chips, the transfer metallurgy is exposed to all of the etching environments. This creates the following problems:
1. Transfer metal lead quality damage in the form of degradation, oxidation, and/or corrosion due to etching environment exposure. Damage to the transfer metal lead is particularly harmful, because it is vital to the interchip and external connection of the module (using T-Connects). In addition, the exposed transfer metallurgy presents an excellent opportunity for water and contaminant ingress between the transfer metallurgy and surrounding insulator.
2. Transfer metal material selection is limited to materials that are compatible with (not susceptible to) the etchants used. For example, the transfer metal cannot be aluminum (Al) because there are Al structures (chip metallurgy) in the kerf region that are etched using an Al etch; therefore, etching these structures would result in etching of the transfer metallurgy as well.
3. Each time the side surface is reworked, the etching processes must be repeated. This results in additional fabrication costs, as well as additional exposure to "aggressive" etching environments. This exposure may impact the long term reliability of the module, particularly that of the transfer metal leads and associated T-Connects.
4. The rate and efficiency of side surface etching processes are affected by the rate at which etchants are fed to the etching zone (the side surface) and the rate at which etchant is removed from the etching zone. Thus, geometries which restrict or limit the transport of etchant are inherently more difficult to etch, and usually require longer etching times or more concentrated etchant solutions. The etching of kerf structures during side surface processing presents geometries which are small and limit the etchant transport processes.
5. Current side surface kerf etching processes are optimized for specific combinations of kerf materials (chip metallurgy) and transfer metal materials. Thus, if wafers are provided with alternate kerf materials, the entire side surface process may need to be reoptimized. In fact, the situation may arise where the current side surface etching processes are not workable because of the particular combination of kerf materials (chip metallurgy) and transfer metallurgy.
The present invention is directed towards solving these problems.